1. Field of the Invention
This invention relates to a semiconductor fabrication method, and more particularly to a method of fabricating a polysilicon-based load circuit (customarily referred to as poly-load) for SRAM (static random-access memory).
2. Description of Related Art
SRAM is a high-speed volatile semiconductor memory widely used in all various kinds of computers and intelligent electronic devices. An SRAM device is typically composed of a peripheral circuit and a memory cell array. The peripheral circuit includes address decoders that can decode address signals to gain access to the memory cells in the SRAM device. Each SRAM cell is typically composed of an access circuit, a drive circuit, and a load circuit. The circuit structure of a typical SRAM cell is illustratively depicted in the following with reference to FIG. 1.
FIG. 1 is a schematic circuit diagram of a typical 4T (4-transistor) SRAM cell. As shown, the SRAM cell is composed of four MOS transistors T.sub.1, T.sub.2, T.sub.3, T.sub.4 and two resistors R.sub.1, R.sub.2. The two MOS transistors T.sub.1, T.sub.2 in combination constitute a drive circuit for the SRAM cell. The other two MOS transistors T.sub.3, T.sub.4 in combination constitute an access circuit for the SRAM cell, and the two resistors R.sub.1, R.sub.2 in combination constitute a load circuit for the SRAM cell.
The first resistor R.sub.1 has one end connected to the system voltage V.sub.DD and the other end connected to a node A. The second resistor R.sub.2 has one end connected to the system voltage V.sub.DD and the other end connected to a node B. The first MOS transistor T.sub.1 is connected in such a manner that its gate is connected to the node B, its drain is connected to the node A, and its source is connected to the ground voltage V.sub.SS. The second MOS transistor T.sub.2 is connected in such a manner that its gate is connected to the node A, its drain is connected to the node B, and its source is connected to the ground voltage V.sub.SS. The third MOS transistor T.sub.3 is connected in such a manner that its gate is connected to a word line WL, its source (or drain) is connected to a bit line BL, and its drain (or source) is connected to the node A. The fourth MOS transistor T.sub.4 is connected in such a manner that its gate is connected to the word line WL, its source (or drain) is connected to a complementary bit line BL, and its drain (or source) is connected to the node B.
Access to the foregoing SRAM cell is controlled by the access circuit, i.e., the third and fourth MOS transistors T.sub.3, T.sub.4 whose switching states are further controlled by the voltage state on the word line WL. Moreover, the data stored in this SRAM cell is dependent on the switching states of the drive circuit, i.e., the first and second MOS transistors T.sub.1, T.sub.2. The operations accessing this SRAM cell, both write and read, are well known to those skilled in the art of semiconductor memories and not within the spirit and scope of the invention, so description thereof will not be further detailed.
Conventionally, the load circuit of an SRAM cell is fabricated by forming high-resistance polysilicon lines over a semiconductor substrate (thus the name poly-load). A conventional method for fabricating a poly-load for SRAM is illustratively depicted in the following with reference to FIGS. 2A-2D.
FIG. 2A illustrates construction of the SRAM device on a semiconductor substrate 20. A gate 21 is then formed over the substrate 20. Next, an insulating layer 22 is deposited over the entire top surface of the wafer, covering all of the exposed surfaces of the substrate 20 and the gate 21. The insulating layer 22 is then selectively removed through a photolithographic and etching process to form a via hole to expose the gate 21.
FIG. 2B illustrates the subsequent step, in which a thin polysilicon layer 23 is deposited over the insulating layer 22. The polysilicon layer 23 is then defined using conventional lithographic and etch processes to form predetermined interconnecting line and poly-load. After this, a first ion-implantation process is performed on the wafer to dope an impurity element in ion form with a low concentration into the entire polysilicon layer 23 so as to turn the polysilicon layer 23 into a lightly-doped polysilicon layer.
FIG. 2C illustrates the subsequent step, in which a photoresist layer 24 is coated over the wafer. This photoresist layer 24 is selectively removed to form an opening 25 to expose a first part of the polysilicon layer 23, as indicated by the reference numeral 23a, that is predefined to be formed into a conductive interconnecting line, while covering a second part of the same, as indicated by the reference numeral 23b, that is predefined to be formed into the desired poly-load. Subsequently, with the photoresist layer 24 serving as mask, a second ion-implantation process is performed on the wafer so as to further dope an impurity element into the unmasked first part 23a of the polysilicon layer 23, whereby the first part 23a of the polysilicon layer 23 is turned into a highly-doped polysilicon layer. This forms one highly doped polysilicon layer 23a and one lightly doped polysilicon layer 23b from the original polysilicon layer 23. The highly doped polysilicon layer 23a has a low resistance and is used to serve as a conductive interconnecting line. The lightly doped polysilicon layer 23b, on the other hand, has a high resistance and serves as the load circuit of the SRAM cell (i.e., the above-mentioned poly-load). The value of the resistance of the lightly-doped polysilicon layer 23b is dependent on the ion concentration used in the first ion-implantation process and the dimensions (i.e., thickness, width, and length) of the lightly-doped polysilicon layer 23b.
Referring further to FIG. 2D, in the subsequent step, the entire photoresist layer 24 is removed. Next, a dielectric layer 26 is deposited over the entire top surface of the wafer, covering all the exposed surfaces of the highly-doped polysilicon layer 23a and the lightly-doped polysilicon layer 23b. After this, an ILD (Inter Layer Dielectric) layer 27 is deposited over the dielectric layer 26. A densification process is then performed on the ILD layer 27 so as to densify the ILD layer 27 and to activate the impurity in the polysilicon layer 23. This completes the fabrication of the poly-load for one SRAM cell.
Theoretically the value of the resistance of the lightly-doped polysilicon layer 23b (i.e., the poly-load) is dependent on the ion concentration used in the first ion-implantation process and the dimensions, i.e., thickness, width, and length, of the lightly-doped polysilicon layer 23b. However, during the densification process, the impurity ions in the highly-doped polysilicon layer 23a are forced to diffuse toward the lightly-doped polysilicon layer 23b (which is called lateral diffusion), thus causing the lightly-doped polysilicon layer 23b to be reduced in length. This not only causes the resultant poly-load to be undesirably changed in resistance, but also makes the SRAM device unsuitable to be further reduced to a submicron level of integration.
One solution to the foregoing problem is to reduce the concentration of the impurity ions in the highly doped polysilicon layer 23a to a lower level. However, this then causes the resultant conductive interconnecting line to have an increase in sheet resistance, thus leading to the undesired occurrence of a severe IR drop (also called voltage drop) across each memory cell in the SRAM device. This adversely affects the stability of the SRAM device.